Silicon spin qubits encode quantum information in the spin state of one or more electrons (or holes) confined electrostatically in a silicon quantum dot, rather than in a superconducting circuit or a trapped atom. Because they can be fabricated with process steps closely related to conventional semiconductor manufacturing, they are seen as a path toward the very large qubit counts a useful quantum computer will eventually need, without requiring an entirely new fabrication industry.
The platform’s central engineering challenges are less about a single qubit’s quality and more about scale: wiring enough independent control signals from room temperature down to a cryostat without the wiring itself becoming the bottleneck, and connecting qubits that sit at fixed positions on a chip widely enough to run the multi-qubit operations quantum error correction needs.
Related papers
- HRL Quantum Team (Blumoff, Ladd, and Reed, corresponding authors, et al.), “A digitally controlled silicon quantum processing unit”, Nature (2026) — integrates an on-chip cryogenic CMOS controller to eliminate most of the room-temperature control wiring. Covered in 2026-w32.
- Undseth, Meggiato, Wu, Katiraee-Far, Tryputen, de Snoo, Degli Esposti, Scappucci, Greplová, and Vandersypen, “Weight-four parity checks with silicon spin qubits”, Nature 655, 1160–1166 (2026) — uses coherent spin shuttling between fixed “bus stops” to connect qubits widely enough for surface-code parity checks. Covered in 2026-w32.